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| 1 features ? 12.4 specint95, 8.4 specfp95 at 266 mhz (tspc750a) with 1 mb l2 at 133 mhz ? 11.5 specint95, 6.9 specfp95 at 266 mhz (tspc740a) ? 488 mips at 266 mhz ? selectable bus clock (11 cpu bus dividers up to 8x) ? p d typical 4.2 w at 200 mhz, full operating conditions ? nap, doze and sleep modes for power savings ? superscalar (3 instructions per clock cycle) ? 4-gbyte direct addressing range ? 64-bit data and 32-bit address bus interface ? 32 kb instruction and data cache ? six independent execution units and two register files ? write-back and write-through operations ? f int max = 266 mhz ? f bus max = 83.3 mhz ? compatible cmos input / ttl output description the tspc750a and tspc740a microprocessor (after named 750a/740a) are low- power implementations of the powerpc reduced instruction set computer (risc) architecture. the 750a/740a microprocessors? designs are superscalar, capable of issuing three instructions per clock cycle into six independent execution units. the 740a/750a microprocessors use a 2.6/3.3v cmos process technology and maintain full interface compatibility with ttl devices. the 750a/740a provide four software controllable power-saving modes and a thermal assist unit management. the 750a/740a microprocessors have s eparate 32k byte, physically-addressed instruction and data caches and differ onl y in that the 750a features a dedicated l2 cache interface with l2 on-chip tags. both are software and bus-compatible with the powerpc 603 ? and powerpc 604 ? families, and are fully jtag compliant. the tspc740a microprocessor is pin compatible with the tspc603e family. g suffix cbga255 and cbga360 ceramic ball grid array gs suffix ci-cbga255 and ci-cbga360 ceramic ball grid array with solder column interposer (sci) powerpc 750a/740a risc microprocessor family pid8t- 750a/740a specification tspc750a/740a rev. 2128a?hirel?01/02
2 tspc750a/740a 2128a?hirel?01/02 screening this product is manufactured in full compliance with: ? cbga upscreenings based upon atmel-grenoble standards ? full military temperature range (tc = -55 c,+125 c) industrial temperature range (tc = -40 c, +110 c) ? ci-cga versions of tspc740a and tspc750a (planned) simplified block diagram the tspc750a is targeted for low power systems and supports the following power management features ? doze, nap, sleep, and dynamic power management. the tspc750a consists of a processor core and an internal l2 tag combined with a dedi- cated l2 cache interface and a 60x bus. figure 1. tspc750a block diagram contr ol unit completion instruction fetch 32k icache bht/btic dispatch system unit branch unit fxu1 fxu2 gprs rename buffers lsu fpu 32k dcache l2 tags l2 cache biu fprs rename buffers 60x biu 3 tspc750a/740a 2128a?hirel?01/02 general parameters the general parameters of the 750a/740a are the following: features except l2 cache interface that is not supported by the powerpc version, the major fea- tures implemented in the powerpc 750a architecture are as follows: level 2 (l2) cache interface (not implemented on tspc740a) ? internal l2 cache controller and 4k-entry tags; external data srams ? 256k, 512k, and 1-mbyte 2-way set associative l2 cache support ? copy-back or write-through data cache (on a page basis, or for all l2) ? 64-byte (256k/512k) and 128-byte (1-mbyte) sectored line size ? supports flow-through (reg-buf) synchronous burst srams, pipelined (reg-reg) synchronous burst srams, and pipelined (reg-reg) late-write synchronous burst srams ? core-to-l2 frequency divisors of 1, 1.5, 2, 2.5, and 3 supported branch processing unit ? four instructions fetched per clock ? one branch processed per cycle (plus resolving 2 speculations) ? up to 1 speculative stream in execution, 1 additional speculative stream in fetch ? 512-entry branch history table (bht) for dynamic prediction ? 64-entry, 4-way set associative branch target instruction cache (btic) to minimize branch delay slots dispatch unit ? full hardware detection of dependencies (resolved in the execution units) ? dispatch two instructions to six independent units (system, branch, load/store, fixed- point unit 1, fixed-point unit 2, or floating-point) ? serialization control (predispatch, postdispatch, execution serialization) load/store unit ? one cycle load or store cache access (byte, half-word, word, double-word) ? effective address generation ? hits under misses (one outstanding miss) ? single-cycle misaligned access within double word boundary ? alignment, zero padding, sign extend for integer register file ? floating-point internal format conversion (alignment, normalization) ? sequencing for load/store multiples and string operations ? store gathering ? cache and tlb instructions technology 0.29 mm cmos, five-layer metal die size 7.56 mm x 8.79 mm (67 mm 2 ) transistor count 6.35 million logic design fully-static packages l2 740a: surface mount 255 ceramic ball grid array (cbga) and column interposer ceramic grid array ci-cga without l2interface 750a: surface mount 360 ceramic ball grid array (cbga) and column interposer ceramic grid array ci-cga with l2 interface core power supply 2.6v 100 mv i/o power supply 3.3v 5% v dc 4 tspc750a/740a 2128a?hirel?01/02 ? big- and little-endian byte addressing supported ? misaligned little-endian support in hardware fixed-point units ? fixed-point unit 1 (fxu1)-multiply, divide, shift, rotate, arithmetic, logical ? fixed-point unit 2 (fxu2)-shift, rotate, arithmetic, logical ? single-cycle arithmetic, shift, rotate, logical ? multiply and divide support (multi-cycle) ? early out multiply bus interface ? compatible with 60x processor interface ? 32-bit address bus ? 64-bit data bus ? bus-to-core frequency multipliers of 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x, 8x supported decode ? register file access ? forwarding control ? partial instruction decode floating-point unit ? support for ieee-754 standard single- and double-precision floating-point arithmetic ? 3 cycle latency, 1 cycle throughput, single-precision multiply-add ? 3 cycle latency, 1 cycle throughput, double-precision add ? 4 cycle latency, 2 cycle throughput, double-precision multiply-add ? hardware support for divide ? hardware support for denormalized numbers ? time deterministic non-ieee mode system unit ? executes cr logical instructions and miscellaneous system instructions ? special register transfer instructions cache structure ? 32k, 32-byte line, 8-way set associative instruction cache ? 32k, 32-byte line, 8-way set associative data cache ? single-cycle cache access ? pseudo-lru replacement ? copy-back or write-through data cache (on a page per page basis) ? supports all powerpc memory coherency modes ? non-blocking instruction and data cache (one outstanding miss under hits) ? no snooping of instruction cache memory management unit ? 128 entry, 2-way set associative instruction tlb ? 128 entry, 2-way set associative data tlb ? hardware reload for tlbs ? 4 instruction bats and 4 data bats ? virtual memory support for up to 4 hexabytes (2 52 ) of virtual memory ? real memory support for up to 4 gigabytes (2 32 ) of physical memory 5 tspc750a/740a 2128a?hirel?01/02 testability ?lssd scan design ?jtag interface integrated power management ? low-power 2.6/3.3v design ? three static power saving modes: doze, nap, and sleep ? automatic dynamic power reduction when internal functional units are idle integrated thermal management assist unit ? on-chip thermal sensor and control logic ? thermal management interrupt for software regulation of junction temperature. reliability and serviceability ? parity checking on 60x and l2 cache buses pin assignments tspc740a package the pinout of the tspc740a, 255 cbga and ci-cga packages as viewed from the top surface. 6 tspc750a/740a 2128a?hirel?01/02 figure 2. pinout of tspc740a, cbga and ci-cga packages as viewed from the top surface tspc750a package the pinout of the tspc750a, 360 cbga and ci-cga packages as viewed from the top surface. a b c d e f g h j k l m n p r t 12 3 4 5678 91011121314 1516 not to scale not to scale view view die substrate encapsulant die substrate assembly encapsulant cbga255 ci-cga255 7 tspc750a/740a 2128a?hirel?01/02 figure 3. pinout of tspc750a, cbga and ci-bga packages as viewed from the top surface pinout listings a b c d e f g h j k l m n p r t 123456789101112131415 16 not to scale 1718 19 u v w s23670w002 l20vdd l20vdd 0vdd 0vdd 12lh pin a1 index gnd gnd vdd vdd die substrate assembly encapsulant die substrate assembly encapsulant cbga360 ci- cga360 not to scale view view tsxp750avgu table 1. pinout listing for the tspc740a, 255 cbga and ci-cga packages signal name pin number active i/o a[0-31] c16, e4, d13, f2, d14, g1, d15, e2, d16, d4, e13, g2, e15, h1, e16, h2, f13, j1, f14, j2, f15, h3, f16, f4, g13, k1, g15, k2, h16, m1, j15, p1 high i/o aack l2 low input abb k4 low i/o ap[0-3] c1, b4, b3, b2 high i/o artry j4 low i/o 8 tspc750a/740a 2128a?hirel?01/02 avdd a10 -- bg l1 low input br b6 low output ci e1 low output ckstp_in d8 low input ckstp_out a6 low output clk_out d7 -output dbb j14 low i/o dbg n1 low input dbdis h15 low input dbwo g4 low input dh[0-31] p14, t16, r15, t15, r13, r12, p11, n11, r11, t12, t11, r10, p9, n9, t10, r9, t9, p8, n8, r8, t8, n7, r7, t7, p6, n6, r6, t6, r5, n5, t5, t4 high i/o dl[0-31] k13, k15, k16, l16, l15, l13, l14, m16, m15, m13, n16, n15, n13, n14, p16, p15, r16, r14, t14, n10, p13, n12, t13, p3, n3, n4, r3, t1, t2, p4, t3, r4 high i/o dp[0-7] m2, l3, n2, l4, r1, p2, m4, r2 high i/o drtry g16 low input gbl f1 low i/o gnd c5, c12, e3, e6, e8, e9, e11, e14, f5, f7, f10, f12, g6, g8, g9, g11, h5, h7, h10, h12, j5, j7, j10, j12, k6, k8, k9, k11, l5, l7, l10, l12, m3, m6, m8, m9, m11, m14, p5, p12 -- hreset a7 low input int b15 low input l1_tstclk (1) d11 high input l2_tstclk (1) d12 high input lssd_mode (1) b10 low input mcp c13 low input nc (no-connect) b7, b8, c3, c6, c8, d5, d6, h4, j16, a4, a5, a2, a3, b1, b5 - - ovdd c7, e5, e7, e10, e12, g3, g5, g12, g14, k3, k5, k12, k14, m5, m7, m10, m12, p7, p10 -- pll_cfg[0-3] a8, b9, a9, d9 high input qack d3 low input qreq j3 low output rsrv d1 low output smi a16 low input sreset b14 low input sysclk c9 -input table 1. pinout listing for the tspc740a, 255 cbga and ci-cga packages (continued) signal name pin number active i/o 9 tspc750a/740a 2128a?hirel?01/02 notes: 1. these are test signals for factory use only and must be pulled up to ov dd for normal machine operation. 2. ov dd inputs supply power to the i/o drivers and v dd inputs supply power to the processor core. 3. internally tied to gnd in the tspc740a cbga package to indicate to the power supply that a low-voltage processor is present. this signal is not a power supply input. ta h14 low input tben c2 high input tbst a14 low i/o tck c11 high input tdi a11 high input tdo a12 high output tea h13 low input tlbisync c4 low input tms b11 high input trst c10 low input ts j13 low i/o tsiz[0-2] a13, d10, b12 high output tt[0-4] b13, a15, b16, c14, c15 high i/o wt d2 low output vdd 2 f6, f8, f9, f11, g7, g10, h6, h8, h9, h11, j6, j8, j9, j11, k7, k10, l6, l8, l9, l11 -- voltdet 3 f3 high output table 1. pinout listing for the tspc740a, 255 cbga and ci-cga packages (continued) signal name pin number active i/o table 2. pinout listing for the tspc750a, 360 cbga and ci-cga packages signal name pin number active i/o a[0-31] a13, d2, h11, c1, b13, f2, c13, e5, d13, g7, f12, g3, g6, h2, e2, l3, g5, l4, g4, j4, h7, e1, g2, f3, j7, m3, h3, j2, j6, k3, k2, l2 high i/o aack n3 low input abb l7 low i/o ap[0-3] c4, c5, c6, c7 high i/o artry l6 low i/o avdd a8 -- bg h1 low input br e7 low output ckstp_out d7 high output ci c2 low output ckstp_in b8 high input clkout e3 -output dbb k5 low i/o 10 tspc750a/740a 2128a?hirel?01/02 dbdis g1 low input dbg k1 low input dbwo d1 low input dh[0-31] w12, w11, v11, t9, w10, u9, u10, m11, m9, p8, w7, p9, w9, r10, w6, v7, v6, u8, v9, t7, u7, r7, u6, w5 , u5, w4, p7, v5, v4, w3, u4, r5 high i/o dl[0-31] m6, p3, n4, n5, r3, m7, t2, n6, u2, n7, p11, v13, u12, p12, t13, w13, u13, v10, w8, t11, u11, v12, v8, t1, p1, v1, u1, n1, r2, v3, u3, w2 high i/o dp[0-7] l1, p2, m2, v2, m1, n2, t3, r1 high i/o drtry h6 low input gbl b1 low i/o gnd d10, d14, d16, d4, d6, e12, e8, f4, f6, f10, f14, f16, g9, g11, h5, h8, h10, h12, h15, j9, j11, k4, k6, k8, k10, k12, k14, k16, l9, l11, m5, m8, m10, m12, m15, n9, n11, p4, p6, p10, p14, p16, r8, r12, t4, t6, t10, t14, t16 -- hreset b6 low input int c11 low input l1_tstclk (1) f8 high input l2addr[0-16] l17, l18, l19, m19, k18, k17, k15, j19, j18, j17, j16, h18, h17, j14, j13, h19, g18 high output l2avdd l13 -- l2ce p17 low output l2clkouta n15 low output l2clkoutb l16 low output l2data[0-63] u14, r13, w14, w15, v15, u15, w16, v16, w17, v17, u17, w18, v18, u18, v19, u19, t18, t17, r19, r18, r17, r15, p19, p18, p13, n14, n13, n19, n17, m17, m13, m18, h13, g19, g16, g15, g14, g13, f19, f18, f13, e19, e18, e17, e15, d19, d18, d17, c18, c17, b19, b18, b17, a18, a17, a16, b16, c16, a14, a15, c15, b14, c14, e13 high i/o l2dp[0-7] v14, u16, t19, n18, h14, f17, c19, b15 high i/o l2ovdd d15, e14, e16, h16, j15, l15, m16, p15, r14, r16, t15, f15 - - l2sync_in l14 high input l2sync_out m14 high output l2_tstclk (1) f7 high input l2we n16 low output l2zz g17 high output lssd_mode (1) f9 low input mcp b11 low input nc (no-connect) b3, b4, b5, a19, w19, w1, k9, k11 (4) , k19 (4) -- ovdd d5, d8, d12, e4, e6, e9, e11, f5, h4, j5, l5, m4, p5, r4, r6, r9, r11, t5, t8, t12 -- table 2. pinout listing for the tspc750a, 360 cbga and ci-cga packages (continued) signal name pin number active i/o 11 tspc750a/740a 2128a?hirel?01/02 notes: 1. these are test signals for factory use only and must be pulled up to ov dd for normal machine operation. 2. ov dd inputs supply power to the i/o drivers and v dd inputs supply power to the processor core. 3. internally tied to l2ovdd in the tspc750a packages atmel-grenoble to indicate the power present at the l2 cache inter- face. this signal is not a power supply input. caution: this is different from the tspc740a packages. 4. these pins are reserved for potential future use as additional l2 address pins. pll_cfg[0-3] a4, a5, a6, a7 high input qack b2 low input qreq j3 low output rsrv d3 low output smi a12 low input sreset e10 low input sysclk h9 -input ta f1 low input tben a2 high input tbst a11 low i/o tck b10 high input tdi b7 high input tdo d9 high output tea j1 low input tlbisync a3 low input tms c8 high input trst a10 low input ts k7 low i/o tsiz[0-2] a9, b9, c9 high output tt[0-4] c10, d11, b12, c12, f11 high i/o wt c3 low output vdd (2) g8, g10, g12, j8, j10, j12, l8, l10, l12, n8, n10, n12 - - voltdet (3) k13 high output table 2. pinout listing for the tspc750a, 360 cbga and ci-cga packages (continued) signal name pin number active i/o 12 tspc750a/740a 2128a?hirel?01/02 signal description figure 4. tspc750a microprocessor signal groups br bg abb ts tt[0-4] ap[0-3] tbst ts1z[0-2] gbl wt ci aack artry dbg dbwo dbb l2addr 160 l2data 063 l2dp 07 l2clkout ab l2we a[0-31] l2sync_out l2sync_in int smi mcp hreset ckstp_in ckstp_out sysclk, pll_cfg 03 4 17 64 8 factory test jt ag:cop address arbitration address start address bus transfer attribute address termination data arbitra tion l2 cache address/ dat a l2 cache clock/control interrupts reset clock control test interface 1 1 2 1 1 1 1 1 1 5 3 1 1 1 1 1 32 4 5 3 1 1 1 1 1 1 d 063 data transfer dp 07 dbdis ta data termina tion drtry tea tspc750a l2av dd l2v dd sreset 1 1 rsr v tben tlbisync qreq qack processor status control clk_out 1 1 1 1 1 1 1 1 v dd v dd (i:o) av dd l2ce l2zz not supported in the tspc740a 1 1 8 1 1 1 1 64 13 tspc750a/740a 2128a?hirel?01/02 scope this drawing describes the specific requirements for the microprocessor tspc750a, in compliance with atmel-grenoble standard screening. applicable documents 1. mil-std-883: test methods and procedures for electronics. 2. mil-prf-38535 appendix a: general specifications for microcircuits. requirements general the microcircuits are in accordance with t he applicable documents and as specified herein. design and construction terminal connections depending on the package, the terminal connections shall be is shown in table 1, table 2 and figure 4. absolute maximum rating notes: 1. functional and tested operating conditions are given in table 4. absolute maximum ratings are stress ratings only, and func- tional operation at the maximums is not guaranteed. stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. caution: v in must not exceed ov dd by more than 0.3v at any time including during power-on reset. 3. caution: ov dd must not exceed v dd /av dd by more than 1.2v at any time including during power-on reset. 4. caution: v dd /av dd must not exceed ov dd by more than 0.4v at any time including during power-on reset. 5. caution: v in may overshoot/undershoot to a voltage and for a maximum duration as shown in figure 5. table 3. absolute maximum ratings characteristic symbol value unit core supply voltage v dd -0.3 to 2.75 (4) v pll supply voltage av dd -0.3 to 2.75 (4) v l2 dll supply voltage l2av dd -0.3 to 2.75 (4) v 60x bus supply voltage ov dd -0.3 to 3.6 (3.5) v l2 bus supply voltage l2ov dd -0.3 to 3.6 (3.5) v input voltage v in -0.3 to 3.6 (2) v storage temperature range t stg -55 to 150 c 14 tspc750a/740a 2128a?hirel?01/02 figure 5 shows the allowable undershoot and overshoot voltage on the tspc750a and tspc 740a. figure 5. overshoot/undershoot voltage recommended operating conditions note: 1. these are the recommended and tested operating conditions. proper device operation outside of these conditions is not guaranteed. 4 v (l2) ov dd + 5% (l2) ov dd gnd 1.0v gnd 0.3v gnd v ih not to exceed 10% of t sysclk v il table 4. recommended operating conditions characteristic symbol value unit core supply voltage v dd 2.5 to 2.7 v pll supply voltage av dd 2.5 to 2.7 v l2 dll supply voltage l2av dd 2.5 to 2.7 v 60x bus supply voltage ov dd 3.135 to 3.465 v l2 bus supply voltage l2ov dd 3.135 to 3.465 v input voltage v in gnd to ov dd v junction temperature t j -55 to +125 c 15 tspc750a/740a 2128a?hirel?01/02 thermal characteristics the board designer can choose between several types of heat sinks to place on the tspc750a. there are several commercially-available heat sinks for the tspc750a provided by the following vendors: for the exposed-die packaging technology, s hown in table 5, the intrinsic conduction thermal resistance paths are as follows: ? the die junction-to-case (or top-of-die for exposed silicon) thermal resistance ? the die junction-to-ball thermal resistance figure 6 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board. heat generated on the active side of the chip is conducted through the silicon, then through the heat sink attach material (or thermal interface material), and finally to the heat sink where it is removed by forced-air convection. since the silicon thermal resistance is quite small, for a first-order analysis, the tempera- ture drop in the silicon may be neglected. thus, the heat sink attach material and the heat sink conduction/convective thermal resistances are the dominant terms. figure 6. c4 package with heat sink mounted to a printed-circuit board thermal management assistance the tspc750a incorporates a thermal management assist unit (tau) composed of a thermal sensor, digital-to-analog converter, comparator, control logic, and dedicated special-purpose registers (sprs). specifications for the thermal sensor portion of the tau are found in table 6. more information on the use of this feature is given in the mpc750a risc microprocessor user?s manual. table 5. package thermal characteristics characteristic symbol value rating cbga and ci-cga packages thermal resistance, junction-to-case thermal resistance (typical) jc 0.03 c/w cbga package thermal resistance, die junction-to-lead thermal resistance (typical) jb 3.8 c/w ci-cga package thermal resistance, die junction-to-lead thermal resistance (typical) jb 4 c/w external resistance external resistance internal resistance (note the internal versus external package resistance) radiation convection radiation convection heat sink printed circuit board thermal interface material package/leads die junction die/package 16 tspc750a/740a 2128a?hirel?01/02 notes: 1. the temperature is the junction temperature of the die. the thermal assist unit?s raw output does not indicate an absol ute temperature, but it must be interpreted by software to derive the absolute junction temperature. for information about the use and calibration of the tau, see the motorola application note an1800/d ?programming the thermal assist unit in the mpc750a microprocessor. this specification reflects the temperature span supported by design. 2. the comparator settling time value must be converted into the number of cpu clocks that need to be written into the thrm3 spr. 3. guaranteed by design and characterization. thermal management information this section provides thermal management information for the ceramic ball grid array (cbga) package for air-cooled applications. proper thermal control design is primarily dependent upon the system-level design the hea t sink, airflow and thermal interface material. to reduce the die-junction temper ature, heat sinks may be attached to the package by several methods-adhesive, spring clip to holes in the printed circuit board or package, and mounting clip and screw assembly; see figure 7. this spring force should not exceed 5.5 pounds of force. figure 7. package exploded cross-sectional view with several heat sink options ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost. table 6. thermal sensor specifications v dd = av dd = l2av dd = 2.6 v dc 100 mv, ov dd = l2ov dd = 3.3 5% v dc , gnd = 0 v dc , 0 t j < +125 c num characteristic min max unit notes 1 temperature range 0 127 c1 2 comparator settling time 20 - s 2 3 resolution 4 - c3 adhesive or thermal interface material heat sink cbga package heat sink clip printed circuit board option 17 tspc750a/740a 2128a?hirel?01/02 adhesives and thermal interface materials figure 8. thermal performance of select thermal interface material a thermal interface material is recommended at the package lid-to-heat sink interface to minimize the thermal contact resistance. fo r those applications where the heat sink is attached by spring clip mechanism, figure 8 shows the thermal performance of three thin-sheet thermal-interface materials (silicone, graphite/oil, floroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure. as shown, the perfor- mance of these thermal interface materials improves with increasing contact pressure. the use of thermal grease significantly reduces the interface thermal resistance. that is, the bare joint results in a thermal resistance approximately 7 times greater than the ther- mal grease joint. heat sinks are attached to the package by means of a spring clip to holes in the printed- circuit board (see figure 7). this spring force should not exceed 5.5 pounds of force. therefore, the synthetic grease offers the best thermal performance, considering the low interface pressure. the board designer can choose between several types of thermal interface. heat sink adhesive materials should be selected based upon high conductivity, yet adequate mechanical strength to meet equipment shock/vibration requirements. 0 0.5 1 1.5 2 0 102030405060708 0 silicone sheet (0.006 inch) bare joint floroether oil sheet (0.007 inch) graphite/oil sheet (0.005 inch) synthetic grease contact pressure (psi) specific thermal resistance (kin2/w) 18 tspc750a/740a 2128a?hirel?01/02 heat sink selection example for preliminary heat sink sizing, the die-junction temperature can be expressed as follows: t j = t a + t r + ( jc + int + sa ) * p d where: t j is the die-junction temperature t a is the inlet cabinet ambient temperature t r is the air temperature rise within the computer cabinet jc is the junction-to-case thermal resistance int is the adhesive or interface material thermal resistance sa is the heat sink base-to-ambient thermal resistance p d is the power dissipated by the device during operation the die-junction temperatures (t j ) should be maintained less than the value specified in table 4. the temperature of the air cooling the component greatly depends upon the ambient inlet air temperature and the air temperature rise within the electronic cabinet. an electronic cabinet inlet-air temperature (t a ) may range from 30 to 40 c. the air temperature rise within a cabinet (t r ) may be in the range of 5 to 10 c. the thermal resistance of the thermal interface material ( int ) is typically about 1 c/w. assuming a t a of 30 c, a t r of 5 c, a cbga package jc = 2.2, and a power consump- tion (p d ) of 4.5 watts, the following expression for t j is obtained: die-junction temperature: t j = 30 c + 5 c + (2.2 c/w + 1.0 c/w + sa ) * 4.5 w for a thermalloy heat sink #2328b, the heat sink-to-ambient thermal resistance ( sa ) versus airflow velocity is shown in figure 9. figure 9. thermalloy #2328b heat sink-to-ambient thermal resistance versus airflow velocity 1 3 5 7 8 0.511.522.53 3.5 thermalloy #2328b pinfin heat sink approach air velocity (m/s) heat sink thermal resistance (c/w) (25 x 28 x 15 mm) 2 4 6 19 tspc750a/740a 2128a?hirel?01/02 assuming an air velocity of 0.5 m/s, we have an effective r sa of 7 c/w, thus t j = 30c + 5c + (2.2c/w +1.0c/w + 7c/w) * 4.5 w, resulting in a die-junction temperature of approximately 81c which is well within the maximum operating temperature of the component. other heat sinks offered by chip coolers, ierc, thermalloy, wakefield engineering, and aavid engineering offer different heat sink-to-ambient thermal resistances, and may or may not need air flow. though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common figure-of-merit used for comparing the thermal performance of various microelectronic packaging te chnologies, one should exerci se caution when only using this metric in determining thermal management because no single parameter can ade- quately describe three-dimensional heat flow. the final die-junction operating temperature, is not only a function of the component-level thermal resistance, but the system-level design and its operating conditions. in addition to the component?s power consumption, a number of factors affect the final operating die-junction temperature-air- flow, board population (local heat flux of adjacent components), heat sink efficiency, heat sink attach, heat sink placement, next-level interconnect technology, system air temperature rise, altitude, etc. due to the complexity and the many variations of system-level boundary conditions for today?s microelectronic equipment, the combined effects of the heat transfer mecha- nisms (radiation, convection and conduction) may vary widely. for these reasons, we recommend using conjugate heat transfer models for the board, as well as, system-level designs. to expedite system-level thermal analysis, several ?compact? thermal-package models are available within flotherm ? . these are available upon request. power consideration power management the tspc750a provides four power modes, selectable by setting the appropriate con- trol bits in the msr and hido registers. the four power modes are as follows: ? full-power: this is the default power state of the tspc750a. the tspc750a is fully powered and the internal functional units are operating at the full processor clock speed. if the dynamic power management mode is enabled, functional units that are idle will automatically enter a low-power state without affecting performance, software execution, or external hardware. ? doze: all the functional units of the tspc750a are disabled except for the time base/decrementer registers and the bus snooping logic. when the processor is in doze mode, an external asynchronous interrupt, a system management interrupt, a decrementer exception, a hard or soft reset, or machine check brings the tspc750a into the full-power state. the tspc750a in doze mode maintains the pll in a fully powered state and locked to the system external clock input (sysclk) so a transition to the full-power state takes only a few processor clock cycles. ? nap: the nap mode further reduces power consumption by disabling bus snooping, leaving only the time base register and the pll in a powered state. the tspc750a returns to the full-power state upon receipt of an external asynchronous interrupt, a system management interrupt, a decrementer exception, a hard or soft reset, or a machine check input (mcp ). a return to full-power state from a nap state takes only a few processor clock cycles. when the processor is in nap mode, if qack is negated, the processor is put in doze mode to support snooping. 20 tspc750a/740a 2128a?hirel?01/02 ? sleep: sleep mode minimizes power consumption by disabling all internal functional units, after which external system logic may disable the ppl and susclk. returning the tspc750a to the full-power state requires the enabling of the ppl and sysclk, followed by the assertion of an external asynchronous interrupt, a system management interrupt, a hard or soft reset, or a machine check input (mcp ) signal after the time required to relock the ppl. power dissipation notes: 1. these values apply for all valid 60x bus and l2 bus ratios. the values do not include i/o supply power (ov dd and l2ov dd ) or pll/dll supply power (av dd and l2av dd ). ov dd and l2ov dd power is system dependent, but is typically <10% of v dd power. worst case power consumption for av dd = 15 mw and l2av dd = 15 mw. 2. maximum power is measured at v dd = 2.7v 3. typical power is an average value measured at v dd = av dd = l2av dd = 2.6v, ov dd = l2ov dd = 3.3v in a system executing typical applications and benchmark sequences. 4. full-on mode is measured using worst-case instruction sequence. electrical characteristics static characteristics table 7. power consumption v dd = av dd = l2av dd = 2.6 v dc 100 mv, ov dd = l2ov dd = 3.3 5% v dc , gnd = 0 v dc , -55 tj < 125 c processor (cpu) frequency unit notes 200 mhz 233 mhz 266 mhz full-on mode typical 4.2 5.0 5.7 w 1, 3, 4 maximum 6.0 7.0 7.9 w 1, 2, 4 doze mode maximum 1.6 1.8 2.1 w 1, 2 nap mode maximum 250 250 250 mw 1, 2 sleep mode maximum 300 300 300 mw 1, 2 sleep mode?pll and dll disabled typical 305050mw1, 3 maximum 60 100 100 mw 1, 2 table 8. dc electrical specifications v dd = av dd = l2av dd = 2.6 v dc 100 mv, ov dd = l2ov dd = 3.3 5% v dc , gnd = 0 v dc , -55 t j < 125 c characteristic symbol min max unit notes input high voltage (all inputs except sysclk) v ih 2 3.465 v 1,2 input low voltage (all inputs except sysclk) v il gnd 0.8 v sysclk input high voltage cv ih 2.4 3.465 v 1 21 tspc750a/740a 2128a?hirel?01/02 notes: 1. for 60x bus signals, the reference is ov dd while l2ov dd is the reference for the l2 bus signals. 2. excludes test signals (lssd_mode, l1_tstclk, l2_tstclk) and ieee 1149.1 boundary scan (jtag) signals. 3. capacitance is periodically sampled rather than 100% tested. 4. the leakage is measured for nominal ov dd and v dd , or both ov dd and v dd must vary in the same direction (for example, both ov dd and v dd vary by either +5% or -5%). dynamic characteristics after fabrication, parts are sorted by maximum processor core frequency as shown in ?clock ac specifications? and tested for conformance to the ac specifications for that frequency. these specifications are for 200, 233, and 266 mhz processor core frequen- cies. the processor core frequency is determined by the bus (sysclk) frequency and the settings of the pll_cfg[0-3] signals. parts are sold by maximum processor core frequency. clock ac specifications table 9 provides the clock ac timing specifications as defined in figure 9. notes: 1. caution : the sysclk frequency and pll_cfg[0-3] settings must be chosen such that the resulting sysclk (bus) fre- quency, cpu (core) frequency, and pll (vco) frequency do not exceed their respective maximum or minimum operating frequencies. refer to the pll_cfg[0-3] signal description in ?pll configuration,? for valid pll_cfg[0-3] settings 2. rise and fall times for the sysclk input are measured from 0.4 to 2.4v. 3. timing is guaranteed by design and characterization. 4. the total input jitter (short term and long term combined) must be under 150 ps. 5. relock timing is guaranteed by design and characterization. pll-relock time is the maximum amount of time required for pll lock after a stable v dd and sysclk are reached during the power-on reset sequence. this specification also applies when the pll has been disabled and subsequently re-enabled during sleep mode. also note that hreset must be held asserted for a minimum of 255 bus clocks after the pll-relock time during the power-on reset sequence. sysclk input low voltage cv il gnd 0.4 v input leakage current, v in = ov dd i in -30a1, 2 hi-z (off-state) leakage current, v in = ov dd i tsi -30a1, 2,4 output high voltage, i oh = -6 ma v oh 2.4 - v output low voltage, i ol = 6 ma v ol -0.4v capacitance, v in = 0v, f = 1 mhz c in -5.0pf2, 3 table 8. dc electrical specifications v dd = av dd = l2av dd = 2.6 v dc 100 mv, ov dd = l2ov dd = 3.3 5% v dc , gnd = 0 v dc , -55 t j < 125 c characteristic symbol min max unit notes table 9. clock ac timing specifications v dd = av dd = l2av dd = 2.6 v dc 100 mv, ov dd = l2ov dd = 3.3 5% v dc , gnd = 0 v dc , -55 t j < 125 c num characteristic 200 mhz 233 mhz 266 mhz unit notes min max min max min max processor frequency 150 200 150 233 150 266 mhz vco frequency 300 400 300 466 300 533 mhz sysclk frequency 25 83.3 25 83.3 25 83.3 mhz 1 1 sysclk cycle time 12 40 12 40 12 40 ns 2, 3 sysclk rise and fall time - 2 - 2 - 2 ns 2 4 sysclk duty cycle measured at 1.4v 40 60 40 60 40 60 % 3 sysclk jitter - 150 - 150 - 150 ps 4 internal pll relock time -100-100-100s 5 22 tspc750a/740a 2128a?hirel?01/02 figure 10 provides the sysclk input timing diagram. figure 10. sysclk input timing diagram 60x bus input ac specifications table 10 provides the 60x bus input ac timing specifications for the tspc750a as defined in figure 11 and figure 12. input timing specifications for the l2 bus are pro- vided in l2 bus input ac specifications. notes: 1. all input specifications are measured from the ttl level (0.8 to 2.0v) of the signal in question to the 1.4v of the ris ing edge of the input sysclk. input and output timings are measured at the pin. 2. address/data/transfer attribute inputs are compos ed of the following ? a[0- 31], ap[0-3], tt[0-4], tbst , tsiz[0-2], gbl , dh[0-31], dl[0-31], dp[0-7]. 3. all other signal inputs are composed of the following-ts , abb , dbb , artry , bg , aack , dbg , dbwo , ta , drtry , tea , dbdis , hreset , sreset , int , smi , mcp , tben, qack, tlbisync . 4. the setup and hold time is with respect to the rising edge of hreset (see figure 12). 5. t sysclk is the period of the external clock (sysclk) in nanoseconds (ns). the numbers given in the table must be multiplied by the period of sysclk to compute the actual time duration (in nanoseconds) of the parameter in question. 6. guaranteed by design and characterization. 7. this specification is for configuration mode select only. also note that the hreset must be held asserted for a minimum of 255 bus clocks after the pll re-lock time during the power-on reset sequence. vm vm = midpoint voltage (1.4v) 2 3 cvil cvih 1 sysclk vm vm 4 4 table 10. 60x bus input ac timing specifications (1) v dd =av dd = l2av dd = 2.6 v dc 100 mv, ov dd = l2ov dd = 3.3 5% v dc , gnd = 0 v dc , -55 t j < 125 c num characteristic 200, 233, 266 mhz unit notes min max 10a address/data/transfer attribute inputs valid to sysclk (input setup) 2.5 - ns 2 10b all other inputs valid to sysclk (input setup) 3.0 - ns 3 10c mode select input setup to hreset (drtry , tlbisync )8 -t sysclk 4, 5, 6, 7 11a sysclk to address/data/transfer attribute inputs invalid (input hold) 1.0 - ns 2 11b sysclk to all other inputs invalid (input hold) 1.0 - ns 3 11c hreset to mode select input hold (drtry , tlbisync )0-ns4, 6, 7 23 tspc750a/740a 2128a?hirel?01/02 figure 11 provides the input timing diagram for the tspc750a. figure 11. input timing diagram figure 12 provides the mode select input timing diagram for the tspc750a. figure 12. mode select input timing diagram 60x bus output ac specifications table 11 provides the 60x bus output ac timing specifications for the tspc750a as defined in figure 13. output timing specifications for the l2 bus are provided in l2 bus output ac specifications. 11a vm vm = midpoint voltage (1.4v) sysclk 11b 10a 10b all inputs vih hreset 11 c mode pins 10c vih = 2.0v table 11. 60x bus output ac timing specifications (1) v dd = av dd = l2av dd = 2.6 v dc 100 mv, ov dd = l2ov dd = 3.3 5% v dc , gnd = 0 v dc , -55 t j < 125 c, cl = 50 pf(2) num characteristic 200, 233, 266 mhz unit notes min max 12 sysclk to output driven (output enable time) 0.5 - ns 13 sysclk to output valid (ts, abb, artry , dbb )-6.5ns5 14 sysclk to all other outputs valid (all except ts, abb , artry , dbb ) -6.5ns5 15 sysclk to output invalid (output hold) 1.0 - ns 3 16 sysclk to output high impedance (all except abb , artry , dbb )- 6.0 ns 8 17 sysclk to abb , dbb high impedance after precharge - 1.0 t sysclk 4, 6, 8 18 sysclk to artry high impedance before precharge - 5.5 ns 8 24 tspc750a/740a 2128a?hirel?01/02 notes: 1. all output specifications are measured from the 1.4v of the rising edge of sysclk to ttl level (0.8 v or 2.0 v) of the si gnal in question. both input and output timing are measured at the pin. 2. all maximum timing specifications assume c l = 50 pf. 3. this minimum parameter assumes c l = 0 pf. 4. t sysclk is the period of the external bus clock (sysclk) in nanoseconds (ns). the numbers given in the table must be multi- plied by the period of sysclk to compute the actual time duration of the parameter in question. 5. output signal transitions from gnd to 2.0v or ov dd to 0.8v. 6. nominal precharge width for abb and dbb is 0.5 t sysclk . 7. nominal precharge width for artry is 1.0 t sysclk . 8. guaranteed by design and characterization. figure 13. output timing diagram 19 sysclk to artry precharge enable 0.2*t sysclk +1.0 -ns3, 4, 7 20 maximum delay to artry precharge - 1 t sysclk 4, 7 21 sysclk to artry high impedance after precharge - 2 t sysclk 4, 7, 8 table 11. 60x bus output ac timing specifications (continued) (1) v dd = av dd = l2av dd = 2.6 v dc 100 mv, ov dd = l2ov dd = 3.3 5% v dc , gnd = 0 v dc , -55 t j < 125 c, cl = 50 pf(2) num characteristic 200, 233, 266 mhz unit notes min max sysclk 12 15 16 16 all outputs ts artry abb, dbb vm vm vm = midpoint voltage (1.4v) 15 vm 18 14 13 13 17 21 19 20 (except ts, abb, artry, dbb) 25 tspc750a/740a 2128a?hirel?01/02 l2 clock ac specifications notes: 1. l2clk outputs are l2clk_outa, l2clk_outb and l2sync_out pins. the l2 cache interface supports higher frequen- cies when appropriate load conditions have been considered. the l2 i/o drivers have been designed to support a 133 mhz l2 bus loaded with 4 off-the-shelf pipelined synchronous burst srams. running the l2 bus beyond 133 mhz requires tightly coupled customized srams or a multi-chip module (mcm) implementation. the l2clk frequency to core frequency set- tings must be chosen such that the resulting l2clk frequency and core frequency do not exceed their respective maximum or minimum operating frequencies. l2clk_outa and l2clk_outb must have equal loading. 2. the nominal duty cycle of the l2clk is 50% measured at midpoint voltage. 3. the total input jitter (short term and long term combined) must be under 150 ps. 4. the dll re-lock time is specified in terms of l2clks. the number in the table must be multiplied by the period of l2clk to compute the actual time duration in nanoseconds. re-lock timing is guaranteed by design and characterization. 5. the l2cr[l2sl] bit should be set for l2clk frequencies less than 110 mhz. table 12. l2clk output ac timing specifications v dd = av dd = l2av dd = 2.6 v dc 100 mv, ov dd = l2ov dd = 3.3 5% v dc , gnd = 0 v dc , -55 t j < 125 c num characteristic min max unit notes l2clk frequency 80 133 mhz 1, 5 22 l2clk cycle time 7.5 12.5 ns 23 l2clk duty cycle 50 % 2 l2clk jitter 150 ps 3 internal dll-relock time 640 - l2clk 4 26 tspc750a/740a 2128a?hirel?01/02 the l2clk_out timing diagram is shown in figure 14. figure 14. l2clk_out output timing diagram table 13 shows the l2 bus input timing diagrams for the tspc750a. figure 15. l2 bus input timing diagrams vm vm = midpoint voltage (l2ovdd/2) 22 l2clk_outa vm vm 23 vm vm = midpoint voltage (l2ovdd/2) 22 l2clk_outa vm vm 23 l2clk_outb l2 singleended clock mode gnd l2ovdd vm l2clk_outb vm vm vm l2sync_out vm vm vm l2sync_out vm vm l2 differential clock mode vm vm = midpoint voltage (1.4v) l2sync_in 25 24 all inputs 29 30 27 tspc750a/740a 2128a?hirel?01/02 l2 bus input ac specifications the l2 bus input interface ac timing specifications are found in table 13. notes: 1. all input specifications are measured from the ttl level (0.8v or 2.0v) of the signal in question to the midpoint volta ge of the rising edge of the input l2sync_in. input timings are measured at the pins (see figure 15). 2. rise and fall times for the l2sync_in input are measured from 0.4 to 2.4v. l2 bus output ac specifications table 14 provides the l2 bus output inter face ac timing specifications for the tspc750a as defined in figure 16. notes: 1. all outputs are measured from the midpoint voltage of the rising edge of l2sync_in to the ttl level (0.8v or 2.0v) of t he signal in question. the output timings are measured at the pins. 2. the outputs are valid for both single-ended and differential l2clk modes. for flow-thru and pipelined reg-reg synchro- nous burst rams, l2cr[14-15] = 00 is recommended. for pipelined delay-write synchronous burst srams, l2cr[14-15] = 01 is recommended. 3. all maximum timing specifications assume c l = 20 pf. 4. this measurement assumes c l = 5 pf. 5. reserved for future use. table 13. l2 bus input interface ac timing specifications, see note (1) v dd = av dd = l2av dd = 2.6 v dc 100 mv, ov dd = l2ov dd = 3.3 5% v dc , gnd = 0 v dc , -55 t j < 125 c num characteristic processor frequency 200-266 mhz unit notes min max 29, 30 l2sync_in rise and fall time - 1.0 ns 2 24 data and parity input setup to l2sync_in 2.0 - ns 25 l2sync_in to data and parity input hold 0.5 _ ns table 14. l2 bus output interface ac timing specifications see note (1) v dd = av dd = l2av dd = 2.6 v dc 100 mv, ov dd = l2ov dd = 3.3 5% v dc , gnd = 0 v dc , -55 t j < 125 c, cl = 20 pf see note (3) num characteristic l2cr[14-15] is equivalent to: unit notes 00 (2) 01 10 11 min max min max min max min max 26 l2sync_in to output valid - 5.0 - 5.5 - 5.7 - 6 ns 27 l2sync_in to output hold 0.5 - 1.0 - 1,2 - 1,5 - ns 4 28 l2sync_in to high impedance - 4.0 - 4.5 - 4.7 - 5 ns 28 tspc750a/740a 2128a?hirel?01/02 figure 16 shows the l2 bus output timing diagrams for the tspc750a. figure 16. l2 bus output timing diagrams ieee 1149.1 ac timing specifications table 15 provides the ieee 1149.1 (jtag) ac timing specifications as defined in figure 17, figure 18, figure 19, and figure 20. notes: 1. trst is an asynchronous level sensitive signal. the setup time is for test purposes only. 2. non-jtag signal input timing with respect to tck. 3. non-jtag signal output timing with respect to tck. 4. guaranteed by design and characterization. 27 vm vm = midpoint voltage (1.4v) l2sync_in 26 all outputs vm 28 l2data bus table 15. jtag ac timing specifications (independent of sysclk) v dd = av dd = l2av dd = 2.6 v dc 100 mv, ov dd = l2ov dd = 3.3 5% v dc , gnd = 0 v dc , -55 t j < 125 c, c l = 50 pf num characteristic min max unit notes tck frequency of operation 0 33.3 mhz 1 tck cycle time 30 - ns 2 tck clock pulse width measured at 1.4v 15 - ns 3 tck rise and fall times 0 2 ns 4 specification obsolete, intentionally omitted 5trst assert time 25 - ns 1 6 boundary-scan input data setup time 4 - ns 2 7 boundary-scan input data hold time 15 - ns 2 8 tck to output data valid 4 20 ns 3 9 tck to output high impedance 3 19 ns 3, 4 10 tms, tdi data setup time 0 - ns 11 tms, tdi data hold time 12 - ns 12 tck to tdo data valid 4 12 ns 13 tck to tdo high impedance 3 9 ns 4 29 tspc750a/740a 2128a?hirel?01/02 figure 17 provides the jtag clock input timing diagram. figure 17. jtag clock input timing diagram figure 18 provides the trst timing diagram. figure 18. trst timing diagram figure 19 provides the boundary-scan timing diagram. figure 19. boundary-scan timing diagram tck 2 2 1 vm vm vm 3 3 vm = midpoint voltage 5 trst 6 7 8 9 8 tck data inputs data outputs data outputs data outputs input data valid output data valid output data valid 30 tspc750a/740a 2128a?hirel?01/02 figure 20 provides the test access port timing diagram. figure 20. test access port timing diagram preparation for delivery packaging microcircuits are prepared for delivery in accordance with mil-prf-38535. certificate of compliance atmel-grenoble offers a certificate of compliances with each shipment of parts, affirm- ing the products are in compliance either with mil-prf-883 and guaranteeing the parameters not tested at temperature extremes for the entire temperature range. handling mos devices must be handled with certain p recautions to avoid damage due to accu- mulation of static charge. input protection devices have been designed in the chip to minimize the effect of static buildup. however, the following handling practices are recommended: a) devices should be handled on benches with conductive and grounded surfaces. b) ground test equipment, tools and operator. c) do not handle devices by the leads. d) store devices in conductive foam or carriers. e) avoid use of plastic, rubber, or silk in mos areas. f) maintain relative humidity above 50 percent if practical. g) for ci-cga packages, use specific tray to take care of the highest height of the package compared with the regular cbga. 10 11 12 13 12 tck tdi, tms tdo tdo tdo input data valid output data valid output data valid 31 tspc750a/740a 2128a?hirel?01/02 clock relationships choice the tspc750a?s pll is configured by the pll_cfg[0-3] signals. for a given sysclk (bus) frequency, the pll configuration signals set the internal cpu and vco frequency of operation. the pll configuration for the tspc750a is shown in table 16 for nominal frequencies. table 17 provides sample core-to-l2 frequencies. notes: 1. pll_cfg[0?3] settings not listed are reserved. 2. the sample bus-to-core frequencies shown are for reference only. some pll configurations may select bus, core, or vco frequencies which are not useful, not supported, or not tested for by the tspc750a; see ?clock ac specifications,? for valid sysclk and vco frequencies. 3. in pll-bypass mode, the sysclk input signal clocks the internal processor directly, the pll is disabled, and the bus mode is set for 1:1 mode operation. this mode is intended for factory use only. note: the ac timing specifications given in this document do not apply in pll-bypass mode . 4. in clock-off mode, no clocking occurs inside the tspc750a regardless of the sysclk input. table 16. tspc750a microprocessor pll configuration pll_cfg [0-3] sample bus-to-core frequency in mhz (vco frequency in mhz) bus-to- core multiplier core-to vco multiplier bus 25 mhz bus 33.3 mhz bus 40 mhz bus 50 mhz bus 66.6 mhz bus 75 mhz bus 83.3 mhz bus 100 mhz 1000 3x 2x 150 (300) 200 (400) 225 (450) 250 (500) 1110 3.5x 2x 175 (350) 233 (466) 262 (525) 1010 4x 2x 160 (320) 200 (400) 266 (533) 0111 4.5x 2x 150 (300) 180 (360) 225 (450) 1011 5x 2x 166 (333) 200 (400) 250 (500) 1001 5.5x 2x 183 (366) 220 (440) 1101 6x 2x 150 (300) 200 (400) 240 (480) 0101 6.5x 2x 162 (325) 216 (433) 260 (520) 0010 7x 2x 175 (350) 233 (466) 0001 7.5x 2x 187 (375) 250 (500) 1100 8x 2x 200 (400) 266 (533) 0011 pll off/bypass pll off, sysclk clocks core circuitry directly, 1x bus-to-core implied 1111 pll off pll off, no core clocking occurs 32 tspc750a/740a 2128a?hirel?01/02 note: 1. the core and l2 frequencies are for reference only. some configurations may select core or l2 frequencies which are not useful, not supported, or not tested for by the tspc750a; see ?l2 clock ac specifications,? for valid l2clk frequencies. the l2cr[l2sl] bit should be set for l2clk frequencies less than 110 mhz. system design information pll power supply filtering the av dd and l2av dd power signals are provided on the tspc750a to provide power to the clock generation phase-locked loop and l2 cache delay-locked loop respectively. to ensure stability of the internal clock, the power supplied to the av dd input signal should be filtered using a circuit similar to the one shown in figure 21. the circuit should be placed as close as possible to the av dd pin to ensure it filters out as much noise as possible. an identical but separate circuit should be placed as close as possible to the l2av dd pin. figure 21. pll power supply filter circuit decoupling recommendations due to the tspc750a?s dynamic power management feature, large address and data buses, and high operating frequencies, the tspc750a can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. this noise must be prevented from reaching other components in the tspc750a system, and the tspc750a itself requires a clean, tightly regulated source of power. therefore, it is recommended that the system designer place at least one decoupling capacitor at each v dd and ov dd pin (and l2ov dd for the 360 cbga) of the tspc750a. it is also recommended that these decoupling capacitors receive their power from separate v dd , ov dd , and gnd power planes in the pcb, utilizing short traces to minimize inductance. table 17. sample core-to-l2 frequencies core frequency in mhz 1 1.5 2 2.5 3 200 200 133.3 100 80 - 208.3 208 138.6 104 83.3 - 210 210 140 105 84 - 220 220 146.6 110 88 - 225 225 150 112.5 90 - 233.3 233.3 155.5 116.6 93.3 - 240 240 160 120 96 80 266 266 177.3 133 106.4 88.6 v dd 10 ? 10 f 0.1 f av dd (or l2av dd ) gnd 33 tspc750a/740a 2128a?hirel?01/02 these capacitors should vary in value from 220 pf to 10 f to provide both high- and low-frequency filtering, and should be placed as close as possible to their associated v dd or ov dd pins. suggested values for the v dd pins-220 pf (ceramic), 0.01 f (ceramic), and 0.1 f (ceramic). suggested values for the ov dd pins ? 0.01 f (ceramic), 0.1 f (ceramic), and 10 f (tantalum). only smt (surface mount technol- ogy) capacitors should be used to minimize lead inductance. in addition, it is recommended that there be several bulk storage capacitors distributed around the pcb, feeding the v dd and ov dd planes, to enable quick recharging of the smaller chip capacitors. these bulk capacitors should have a low esr (equivalent series resistance) rating to ensure the quick response time necessary. they should also be connected to the power and ground planes through two vias to minimize inductance. suggested bulk capacitors-100 f (avx tps tantalum) or 330 f (avx tps tantalum). connection recommendations to ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. unused active low inputs should be tied to v dd . unused active high inputs should be connected to gnd. all nc (no-connect) signals must remain unconnected. power and ground connections must be made to all external v dd , ov dd , and gnd pins of the tspc750a. external clock routing should ensure that the rising-edge of the l2 clock is coincident at the clk input of all srams and at the l2sync_in input of the tspc750a. the l2clkouta network could be used only, or the l2clkoutb network could also be used depending on the loading, frequency, and number of srams. output buffer dc impedance the tspc750a 60x and l2 i/o drivers were characterized over process, voltage, and temperature. to measure z 0 , an external resistor is connected to the chip pad, either to ov dd or ognd. then, the value of such resistor is varied until the pad voltage is ov dd /2; see figure 22. the output impedance is actually the average of two components, the resistances of the pull-up and pull-down devices. when data is held low, sw1 is closed (sw2 is open), and r n is trimmed until pad = ov dd /2. r n then becomes the resistance of the pull-down devices. when data is held high, sw2 is closed (sw1 is open), and r p is trimmed until pad = ov dd /2. r p then becomes the resistance of the pull-up devices. with a properly designed driver r p and r n are close to each other in value. then z 0 = (r p + r n )/2. 34 tspc750a/740a 2128a?hirel?01/02 figure 22. driver impedance measurement table 18 summarizes the signal impedance results. the driver impedance values were derived by simulation at 65 c. as the process varies, the output impedance will be reduced by several ohms. pull-up resistor requirements the tspc750a requires high-resistive (weak: 10k ? ) pull-up resistors on several control signals of the bus interface to maintain the control signals in the negated state after they have been actively negated and released by the tspc750a or other bus masters. these signals are ts , abb , dbb , and artry . in addition, the tspc750a has one open-drain style output that requires a pull-up resis- tors (weak or stronger: 4.7k ? - 10k ? ) if it is used by the system. this signal is ckstp_out . during inactive periods on the bus, the address and transfer attributes on the bus are not driven by any master and may float in the high-impedance state for relatively long periods of time. since the tspc750a must continually monitor these signals for snoop- ing, this float condition may cause excessive power draw by the input receivers on the tspc750a or by other receivers in the system. it is recommended that these signals be pulled up through weak (10k ? ) pull-up resistors or restored in some manner by the sys- tem. the snooped address and transfer attribute inputs are a[0-31], ap[0-3], tt[0-4], tbst , and gbl . table 18. impedance characteristics v dd = 2.6v, ov dd = 3.3v, tj = 65 c process 60x l2 symbol unit typ 43 38 z 0 ohms ov dd ognd rp rn pad data sw2 sw1 35 tspc750a/740a 2128a?hirel?01/02 the data bus input receivers are normally turned off when no read operation is in progress and do not require pull-up resistors on the data bus. other data bus receivers in the system, however, may require pull-ups, or that those signals be otherwise driven by the system during inactive periods. the data bus signals are dh[0-31], dl[0-31], dp[0-7]. if address or data parity is not used by the system, and the respective parity checking is disabled through hid0, the input receivers f or those pins are disabled, and those pins do not require pull-up resistors and should be left unconnected by the system. if all par- ity generation is disabled through hid0, then all parity checking should also be disabled through hid0, and all parity pins may be left unconnected by the system. no pull-up resistors are normally required for the l2 interface. definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reas onably be expected to result in personal injury. atmel-grenoble customers using or selling these products for use in such appli- cations do so at their own risk and agree to fully indemnify atmel-grenoble for any damages resulting from such improper use or sale. datasheet status validity objective specification this datasheet contains target and goal specification for discussion with customer and application validation. before design phase. target specification this datasheet contains target or goal specification for product development. valid during the design phase. preliminary specification site this datasheet contains preliminary data. additional data may be published later; could include simulation result. valid before characterization phase. preliminary specification site this datasheet contains also characterization results. valid before the industrialization phase. product specification this datasheet contains final product specification. valid for production purpose. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limitin g values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the specification. 36 tspc750a/740a 2128a?hirel?01/02 package mechanical data parameters for the tspc740a the package parameters are as provided in the following list. the package types are 21 x 21 mm, 255-lead cbga and ci-cga. package outline ? 21 x 21 mm interconnects ? 255 (16 x 16 ball array - 1) pitch ? 1.27 mm (50 mil) minimum module height ? 2.45 mm (cbga), 3,45 mm (ci-cga) maximum module height ? 3.00 mm (cbga), 4.00 mm (ci-cga ball or column diameter ? 0.89 mm (35 mil) mechanical dimensions of the tspc740a cbga package figure 23 provides the mechanical dimensions and bottom surface nomenclature of the tspc740a, 255 cbga package. 37 tspc750a/740a 2128a?hirel?01/02 figure 23. mechanical dimensions and bottom surface nomenclature of tspc740a (cbga) notes: a. dimensioning and tolerancing per asme y14.5m, 1994. b. dimensions in millimeters. c. top side a1 corner index is a metalized feature with various shapes. bottom side a1 corner is designated with a ball missing from the array. 0.2 f t 255x a 2x a1 corner b g p n 0.2 2x f e a b c d e f g h j k l m n p r t k e 0.3 t 0.15 d k c h a1 t t m a b c d g h k n p dim min max max min millimeters inches 21.000 bsc 21.000 bsc 0.827 bsc 0.827 bsc 2.45 3.000 0.096 0.118 0.820 0.930 0.032 9.0 9.2 0.354 0.335 0.327 8.5 8.3 0.039 0.031 0.990 0.790 1.270 bsc 0.050 bsc 0.635 bsc 0.025 bsc m 2.00 a1 0.9 1.10 0.035 0.043 0.037 0.074 0.362 1 2 3 4 5678910 1314 11 12 1516 38 tspc750a/740a 2128a?hirel?01/02 mechanical dimensions of the tspc740a ci-cga package figure 24 provides the mechanical dimens ions and bottom surface nomenclature of tspc740a, 255 ci-cga package. figure 24. mechanical dimensions and bottom surface nomenclature of tspc740a (ci-cga) 39 tspc750a/740a 2128a?hirel?01/02 parameters for the tspc750a the package parameters are as provided in the following list. the package type is 25 x 25 mm, 360-lead cbga and ci-cga. package outline ? 25 x 25 mm interconnects ? 360 (19 x 19 ball array - 1) pitch ? 1.27 mm (50 mil) minimum module height ? 2.65 mm (cbga), 3,65 mm (ci-cga) maximum module height ? 3.20 mm (cbga), 4,20 mm (ci-cga) ball or column diameter ? 0.89 mm (35 mil) 40 tspc750a/740a 2128a?hirel?01/02 mechanical dimensions of the tspc750a cbga package figure 25 provides the mechanical dimensions and bottom surface nomenclature of the tspc750a, 360 cbga package. figure 25. mechanical dimensions and bottom surface nomenclature of the tspc750a notes: a. dimensioning and tolerancing per asme y14.5m, 1994. b. dimensions in millimeters. c. top side a1 corner index is a metalized feature with various shapes. bottom side a1 corner is designated with a ball missing from the arra y. d. top side capacitor assembly areas are connected to power planes but not used f t 360x g 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a b c d e f g h j k l m n p r t e 0.3 t 0.15 d c h a1 t 0.2 t 171819 u w v m a b c d g h k n p dim min max max min millimeters inches 25.000 bsc 25.000 bsc 2.65 3.2 0.104 0.126 0.820 0.930 0.032 9.0 9.2 0.354 0.362 0.327 8.5 8.3 0.039 0.031 0.990 0.790 1.270 bsc 0.050 bsc 0.635 bsc 0.025 bsc m 2.00 a1 1.1 1.3 0.2 a 2x a1 corner b p n 0.2 2x f e k k 0.984 bsc 0.043 0.052 0.984 bsc 0.037 0.079 0.335 d3 n2 p2 e3 2.75 3 12,5 14.3 0.108 0.492 0.563 p2 n2 d3 e3 0.118 41 tspc750a/740a 2128a?hirel?01/02 mechanical dimensions of the tspc750a ci-cga package figure 26 provides the mechanical dimens ions and bottom surface nomenclature of tspc750a, 360 ci-cga package figure 26. mechanical dimensions and bottom surface nomenclature of tspc750a (ci-cga) 42 tspc750a/740a 2128a?hirel?01/02 ordering information note: 1. for availability of different versions, contact your atmel sales office. ts pc750a m g u/t 8 x prefix prototype type package g: cbga gs: ci_cga screening level (1) _: standard b/q: mil-std-883, class q b/t: according to mil-std-883 u: upscreening u/t: upscreening + burn-in revision level (1) e: rev. 2.2 obsolete h: rev 3.1 max internal processor speed 8: 200 mhz 10: 233 mhz 12: 266 mhz temperature range: t c m: -55, +125c v: -40 c, +110c (x) l bus divider (to be confirmed) l: any valid pll configuration 43 tspc750a/740a 2128a?hirel?01/02 ? atmel corporation 2002. atmel corporation makes no warranty for the use of its products , other than those expressly cont ained in the company?s standard warranty which is detailed in atmel?s terms and c onditions located on the company?s web site. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specificati ons detailed herein at any time without n otice, and does not make any commitment to update the information contained herei n. no licenses to patents or other intellectual property of at mel are granted by the company in connection with the sale of atmel products, expr essly or by implication. atme l?s products are not authorized for use as critical components in life support devices or systems. atmel headquarters atmel operations corporate headquarters 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 487-2600 europe atmel sarl route des arsenaux 41 casa postale 80 ch-1705 fribourg switzerland tel (41) 26-426-5555 fax (41) 26-426-5500 asia atmel asia, ltd. room 1219 chinachem golden plaza 77 mody road tsimhatsui east kowloon hong kong tel (852) 2721-9778 fax (852) 2722-1369 japan atmel japan k.k. 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel (81) 3-3523-3551 fax (81) 3-3523-7581 memory atmel corporate 2325 orchard parkway san jose, ca 95131 tel 1(408) 436-4270 fax 1(408) 436-4314 microcontrollers atmel corporate 2325 orchard parkway san jose, ca 95131 tel 1(408) 436-4270 fax 1(408) 436-4314 atmel nantes la chantrerie bp 70602 44306 nantes cedex 3, france tel (33) 2-40-18-18-18 fax (33) 2-40-18-19-60 asic/assp/smart cards atmel rousset zone industrielle 13106 rousset cedex, france tel (33) 4-42-53-60-00 fax (33) 4-42-53-60-01 atmel colorado springs 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 atmel smart card ics scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel (44) 1355-803-000 fax (44) 1355-242-743 rf/automotive atmel heilbronn theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel (49) 71-31-67-0 fax (49) 71-31-67-2340 atmel colorado springs 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom atmel grenoble avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel (33) 4-76-58-30-00 fax (33) 4-76-58-34-80 e-mail literature@atmel.com web site http://www.atmel.com 2128a?hirel?01/02 0m atmel ? is the registered trademarks of atmel. powerpc ? is the registered trademark of ibm company. other terms and product names may be the trademarks of others. |
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